Apparatus for testing an integrated circuit in which an input test pattern can be changed with an selected application timing

ABSTRACT

An apparatus for testing an integrated circuit includes a clock generator; a first memory for storing at least one instruction data, and a second memory for storing input data and corresponding expected output data employed in testing. A control unit controls the output of the input data and expected output data in accordance with the content of the instruction data. A counter counts clocks output from the generator. A register circuit stores at least one designated value. A comparing circuit outputs at least one control signal based on the comparison between the designed value and a value of the counter. A circuit defining a first timing data, representing a mode of application of a test pattern, and at least one second timing data, representing a mode of application different from the first timing data, outputs one of the first or second timing data in response to the control signal. A testing circuit applies the input data to the integrated circuit and compares a response signal from the integrated circuit with the expected output data, whereby it is determined whether the integrated circuit is functional or non-functional. By suitably changing the designated value in the register circuit, the mode of application of the test pattern can be easily changed when the test is carried out with an arbitrary test pattern, and at the same time, a change in writing into the second memory is made unnecessary. Thus, a more efficient test is realized.

This application is a continuation of application Ser. No. 526,947 filedMay 23, 1990, now abandoned, which is a continuation of application Ser.No. 187,136 filed Apr. 28, 1988 now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an apparatus for testing an integratedcircuit or a large scale integrated circuit, hereinafter referred to asan LSI tester, and more particularly, to an apparatus which appliespredetermined input test data to an integrated circuit to be tested,hereinafter referred to as a D.U.T., i.e., Device Under Test, andcompares a signal output from the D.U.T. in response to the input testdata with a predetermined expected output test data, to determinewhether the D.U.T. is functional or non-functional.

2. Description of the Related Art

A known typical LSI tester includes a buffer memory, in which input datafor testing a D.U.T., corresponding expected output data, and timingchanging bits for defining an application mode of the input data arestored. This apparatus is constituted in such a manner that a test ofthe D.U.T. is made in accordance with the timing changing bits presetwith respect to each of addresses in the buffer memory. Namely, theapplication mode of the test pattern is fixedly defined based on theorder in which the test pattern to be employed is stored in the buffermemory. Therefore, to change the application mode of the test pattern,the writing into the buffer memory must be inevitably changed, andfurther, to realize a variety of application modes, the capacity of thebuffer memory must be increased.

Accordingly, the LSI tester of the prior art has disadvantages in that;first, it is impossible to freely change the application mode of thetest pattern when the test is carried out with an arbitrary testpattern; second, since a change in writing into the buffer memory isnecessary, the test cannot be efficiently carried out.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an apparatus fortesting an integrated circuit in which, when the circuit is tested withan arbitrary test pattern, an application mode of the test pattern canbe freely changed.

Another object of the present invention is to provide an apparatus fortesting an integrated circuit, by which a change in writing into abuffer memory becomes unnecessary, and thus the test-efficiency isimproved.

The above-mentioned objects of the present invention are attained byproviding, an apparatus for testing an integrated circuit, the apparatusincluding a clock generator for generating a train of clocks with avariable rate of generation; a first memory in which at least oneinstruction data is preset and stored; a second memory in which aplurality of input data and a corresponding plurality of expected outputdata are preset and stored; a control unit connected between the firstmemory and the second memory, for reading the instruction data from thefirst memory in response to each of the clocks output from the clockgenerator and causing the second memory to output the input data and thecorresponding expected output data in accordance with the content of theinstruction data; a counter for sequentially counting the clocks outputfrom the clock generator, one by one; a register circuit in which atleast one designated value is preset and stored; a comparator connectedto the counter and the register circuit, for comparing the designatedvalue in the register circuit with a value of the counter and outputtingat least one control signal based on the result of the comparison; atiming data outputting circuit in which a first timing data representinga first application mode of a test pattern within a time intervaldefined by the variable rate and at least one second timing datarepresenting a second application mode different from the first timingdata are defined, for outputting any one of the first or second timingdata in response to the control signal from the comparator; and a testcircuit connected between the second memory and the integrated circuitto be tested, for applying the input data from the second memory to theintegrated circuit based on the one of the first or second timing dataand comparing a signal, output from the integrated circuit in responseto the input data with the expected output data, corresponding to theinput data, from the second memory, whereby a result of a determinationof whether the integrated circuit is functional or non-functional isindicated.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and features of the present invention will be describedhereinafter in detail by way of preferred embodiments, with reference tothe accompanying drawings in which;

FIG. 1 is a block diagram illustrating the constitution of the LSItester as an example of the prior art;

FIGS. 2a to 2c are waveform diagrams for explaining an operation of theapparatus shown in FIG. 1;

FIG. 3 is a block diagram illustrating the constitution of an LSI testeras an embodiment of the present invention;

FIGS. 4a to 4g are waveform diagrams for explaining an operation of theapparatus shown in FIG. 3;

FIG. 5 is a block diagram illustrating the constitution of the LSItester as another embodiment of the present invention; and

FIGS. 6a to 6d are waveform diagrams for explaining an operation of theapparatus shown in FIG. 5.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

For a better understanding of the preferred embodiments, the problems ofthe prior art will now be explained with reference to FIGS. 1 and 2.

FIG. 1 is a schematic drawing of a constitution of a stored responsetype LSI tester, as an example of the prior art. In FIG. 1, 11 denotes aclock generator for generating a clock at predetermined time intervals,and 12 denotes an address counter, which carries out a sequentialrenewal of addresses in a subsequent buffer memory 13 upon receiving aclock.

In the buffer memory 13, an input data for testing a D.U.T. 17, anexpected output data preset according to the input data, and timingchanging bits for defining an application mode of the input data arestored in accordance with each of addresses 1 to m. The timing changingbits are constituted by two bits in the illustration of FIG. 1, and thuscan define four application modes. The four application modes are storedas data in a timing data outputting circuit 14. In this case, the timingdata outputting circuit 14 outputs two data 1 and 2, e.g., a delay data(D₀) and a pulse width data (W₀) , in accordance with a combination ofbits (0, 0) of a timing changing bit signal input from the buffer memory13.

Reference 15 denotes a waveform formatter, which forms the input datafrom the buffer memory 13 into an actual input test pattern and appliesthat input test pattern to the D.U.T 17 at a timing designated by thetiming data outputting circuit 14. Reference 16 denotes a comparator,which converts the expected output data from the buffer memory 13 intoan actual expected output test pattern, compares a response signaloutput from the D.U.T. 17 in response to the above input test patternwith the expected output test pattern at a timing designated by thetiming data outputting circuit 14, and indicates whether the D.U.T. 17is functional or non-functional, based on a result of that comparison.

FIGS. 2a to 2c show an example of the waveform of the input test patternaccording to the above apparatus of the prior art.

The above apparatus tests the D.U.T. in accordance with the timingchanging bits preset with respect to each of addresses in the buffermemory 13, i.e., each of the test data. Namely, the mode of applicationof the test pattern to be employed is fixedly defined in accordance withthe order in which the test pattern to be employed is stored in thebuffer memory 13.

Accordingly, where a test pattern data stored in the nth order in thebuffer memory 13 is employed and the test is carried out, test patterndata with an application mode different from the application modedefined in the nth order cannot be employed; namely when the test iscarried out with an arbitrary test pattern, the mode of application ofthe test pattern cannot be changed.

To overcome this disadvantage, an enormous amount of timing changingbits must be prepared in the buffer memory; which bits define all of themodes of application of the test patterns required for testing theD.U.T. This means that the capacity of the buffer memory must beincreased, and therefore, the following problems arise. First, since thesize of the buffer memory per se is increased, a correspondinglyincreased memory space in a disc, a CPU memory or the like must besecured. Second, since the amount of information stored in the buffermemory is increased, it becomes difficult to control that information.Third, since more time is required for a change in writing into thebuffer memory, more time is required for the test.

Preferred embodiments of the present invention will now be described indetail with reference to FIGS. 3 to 6.

FIG. 3 illustrates a constitution of an LSI tester as an embodiment ofthe present invention.

In FIG. 3, 20 denotes a controller which reads instruction data presetin an instruction memory 24 in response to clocks CLK output from aclock generator 21 and decodes the content of the instruction data. Thecontroller 20 also changes a rate of generation of the clocks CLK in thegenerator 21 in accordance with data 3 representing a rate informationR₀ in a timing data outputting circuit 28. The clock generator 21generates a train of clocks CLK at a variable generation rate; whichrate is controlled by the controller 20. Reference 22 denotes an addresscounter, which is operated by the clocks CLK from the generator 21 andthe counting operation of which is controlled by the controller 20.Namely, the address counter 22 not only counts the clocks CLK by asequential increment, but also changes the counted value, whichcorresponds to address information in a buffer memory 23, in accordancewith the content of the instruction data decoded by the controller 20.

In the buffer memory 23, input data (input test pattern data) fortesting a D.U.T. 31 and corresponding expected output data (expectedoutput test pattern data) are preset and stored with respect to each ofthe information addresses 1 to m. The buffer memory 23 feeds the inputdata and corresponding expected output data corresponding to theinformation address indicated by the content of the address counter 22to a waveform formatter 29 and a comparator 30, respectively. In thepresent example, the buffer memory 23 has a capacity of 64 K, but theinstruction memory 24, in which a variety of instruction data such asNOP (no operation), JMP (jump), LOOP, LP. END (loop end) and the likeare preset and stored, has a capacity of 4 K. The instruction memory 24functions as a sequence memory for controlling an address sequence inthe buffer memory 23. The instruction data can be arbitrarily changed byan external input; which also applies to the buffer memory 23, withregard to the input data and corresponding expected output data.

Reference 25 denotes a pattern counter, which sequentially counts theclocks CLK output from the clock generator 21, one by one. References26₁, to 26_(n) denote pattern designating registers each having adesignated value preset and stored therein in accordance with anexternal input. References 27₁ and 27_(n) denote comparator provided forthe registers 26₁ to 26_(n) , respectively. Each of the comparator 27₁to 27_(n) compares a designated value stored in the correspondingregister 26₁ to 26_(n) with the content of the counter 25 and, based ona result of the comparison, outputs either a control signal C₀ or acontrol signal C₁ ˜C_(n). For example, the comparator 27₁, compares thecontent of the register 26₁, i.e., the designated value, with thecontent of the counter 25, i.e., a counted value of the clocks CLK,outputs the control signal C₀ when these values do not coincide, andoutputs the control signal C₁ when these values do coincide. In the sameway, the comparator 27.sub. 2 outputs the control signal C₀ when thedesignated value in the register 26₂ and the counted value in thecounter 25 do not coincide, and outputs the control signal C when thesevalues do coincide. This comparing and outputting operation is alsocarried out by the comparators 27₃ ˜27_(n).

In the timing data outputting circuit 28, a plurality of timing data,(n+1) data in the illustrated example, are preset and stored. Each ofthe timing data defines a mode of application of a test pattern data andconsists of three data 1 to 3. Data 1, i.e., D₀ ˜D_(n), represents adelay data (see FIGS. 4c to 4g); data 2, i.e., W₀ ˜W_(n) represents apulse width data; and data 3, i.e., R₀, represents the rate informationfor defining the rate of generation of the clocks CLK in the clockgenerator 21. The timing data outputting circuit 28 outputs the data(D₀, W₀, R₀) as timing data TD when the control signal C₀ output fromone of the comparators 27₁ ˜27_(n) is input thereto. The circuit 28 alsooutputs one of the data (D₁, W₁, R₀), (D₂, W₂, R₀), . . . , (D_(n),W_(n), R₀) as the timing data TD when the control signal C₁, C₂, . . . ,or C_(n) output from one of the comparators 27₁ ˜27_(n) is inputthereto.

The waveform formatter 29 forms the data input from the buffer memory 23into an actual input test pattern and applies the input test pattern tothe D.U.T. 31 at a timing designated by the circuit 28, i.e., at atiming indicated by the output timing data TD. The comparator 30converts the expected output data from the buffer memory 23 into anactual expected output test pattern, compares a response signal outputfrom the D.U.T. 31 in response to the above input test pattern with theexpected output test pattern at a timing indicated by the timing data TDoutput from the circuit 28, and indicates whether the D.U.T. 31 isfunctional or non-functional, based on the result of the comparison.

Next, the operation of the apparatus according to the embodiment shownin FIG. 3 will be explained with reference to the waveform diagramsshown in FIGS. 4a to 4g. Note, to simplify the explanation, only tworegisters 26₁ and 26₂ and the corresponding comparators 27₁ and 27₂ arereferred to in the following text.

Assuming that the rate information R₀ in the timing data outputtingcircuit 28 is preset to a constant value, then, the clock generator 21outputs a train of clocks CLK at a rate of generation corresponding tothe rate information R₀, as shown in FIG. 4a. When the clocks CLK aregenerated, the content of the pattern counter 25 is incrementedsequentially one by one, as shown in FIG. 4b.

Assuming that the contents of both of the registers 26₁ and 26₂ are "0".In this case, since the content of the counter 25 and the contents ofthe registers do not coincide, both of the comparators 27₁ and 27₂output the control signal C₀ to the timing data outputting circuit 28.As a result, the data (D₀, W₀, R₀) as the timing data TD are output fromthe circuit 28 to the waveform formatter 29, and accordingly, theformatter 29 applies the input test pattern as shown in FIG. 4c to theD.U.T. 31.

Alternatively, assuming that the content of the register 26₁ is "1" andthat of the register 26₂ is "0". In the case, when the pattern counter25 counts "1" the comparator 27₁ detects a coincidence between thecontents of the counter 25 and register 26₁ and outputs the controlsignal C₁. As a result, the data (D₁, W₁, R₀) are output as the timingdata TD from the circuit 28 to the waveform formatter 29, andaccordingly, the formatter 29 applies the input test pattern as shown inFIG. 4d; to the D.U.T. 31. Compared with FIG. 4c, the mode ofapplication of the test pattern is changed only when the first testpattern is employed and the test is carried out, i.e., only when thecontent of the pattern counter 25 is "1".

In the same way, assuming that the content of the register 26₁ is "2"and that of the register 26₂ is "0", the input test pattern as shown inFIG. 4e can be realized, and assuming that the content of the register26₁ is "k" and that of the register 26₂ is "0", the input test patternas shown in FIG. 4f can be realized.

Therefore, when the content of the register 26₁ and that of the register26₂ are preset to different values, still another application mode canbe realized. For example, assuming that the content of the register 26₁is "1" and that of the register 26₂ is "3", when the first test patternis employed and the test is carried out, i.e., when the content of thepattern counter 25 is "1", the comparator 27₁ outputs the control signalC₁, so that the circuit 28 outputs the data (D₁, W₁, R₀) to the waveformformatter 29 as the timing data TD.

Alternatively, when the third test pattern is employed and the test iscarried out, i.e., when the content of the pattern counter 25 is "3",the comparator 27₂ outputs the control signal C₂, so that the circuit 28outputs the data (D₂, W₂, R₀) to the waveform formatter 29 as the timingdata TD. Also, when other test patterns except for the first and thirdtest patterns are employed and the tests are carried out, i.e., when thecontent of the pattern counter 25 is not "1" or "3", both of thecomparators 27₁ and 27₂ output the control signal C₀, so that thecircuit 28 outputs the data (D₀, W₀, R₀) to the formatter 29 as thetiming data TD, and thus the input test pattern as shown in FIG. 4g isapplied to the D.U.T. 31.

As explained above, by suitably selecting the values preset in thepattern designating registers 26₁ and 26₂, the mode of application ofthe test pattern can be easily changed when the test is carried out withan arbitrary test pattern. Also, it is unnecessary to provide the buffermemory 23 with the timing changing bits, as in the prior art (see FIG.1), a change in writing into the buffer memory for defining theapplication mode of the test pattern becomes unnecessary, andaccordingly, an efficient test can be realized.

Although, in the above explanation, reference is made to two registers26₁ and 26₂ and the corresponding comparators 27₁ and 27₂, it isapparent to those skilled in the art that a variety of modes ofapplication of the test pattern can be realized by a suitable selectionof the values to be preset in the registers 26₁ ˜26_(n).

FIG. 5 illustrates a construction of the LSI tester as anotherembodiment of the present invention.

The apparatus shown in FIG. 5 provides a window designation type LSItester. Namely, in this apparatus the application mode can be changed insuccession with respect to the test pattern data corresponding toaddresses within a certain range in the buffer memory 23.

The differences between the apparatus of FIG. 5 and that of FIG. 3 areas follows; the registers 26₁ ˜26_(n) are replaced by pairs of registers36A₁ and 36B₁, 36A₂ and 36B₂, . . . , or 36A_(n) and 36B_(n), and thecomparators 27₁ ˜27_(n), are replaced by comparators 37₁, 37₂, . . . ,or 37_(n). Other elements are the same as those shown in FIG. 3, andthus an explanation thereof will be omitted.

In the constitution of FIG. 5, each of the registers 36A₁ ˜36A_(n)stores a designated value for indicating the beginning of a change inthe mode of application of the test pattern, and each of the registers36B₁ ˜36B_(n) stores a designated value for indicating the end of thechange. Each of the comparators 37₁ ˜37_(n) compares designated valuesstored in the corresponding registers with the content of the counter25, and based on a result of the comparison, outputs a control signalC₀, C_(al) ˜C_(an), or C_(bl) ˜C_(bn). For example, the comparator 37₁outputs the control signal C_(al) when the contents of the counter 25and that of the register 36A₁ coincide, and outputs the control signalC_(bl) when the content of the counter 25 and that of the register 36B₁coincide. When the content of the counter 25 and the content of theregister 36A₁ or 36B₁ do not coincide, the comparator 37₁ outputs thecontrol signal C₀ . As a result, the circuit 28 outputs the data (D₀,W₀, R₀) as the timing data TD in response to the control signal C₀. Whenone of the control signals C_(al) ˜C_(an) is input, the circuit 28outputs one of the data (D₁, W₁, R₀), (D₂, W₂, R₀), . . . , and (D_(n),W_(n), R₀) as the timing data TD, and the timing data TD output inresponse to one of the control signals C_(al) ˜C_(an) is maintaineduntil one of the control signals C_(bl) ˜C_(bn) is input to the circuit28. Namely, when one of the control signals C_(bl) ˜C_(bn) is input, thecircuit 28 outputs the original data (D₀, W₀, R₀) as the timing data TD.

In the following explanation, reference is made to only a pair ofregisters 36A₁ and 36B₁ and the corresponding comparator 37₁, forsimplicity. According to the apparatus shown in FIG. 5, the applicationmode (D₀, W₀, R₀) to (D₁, W₁, R₀) can be changed when the test patterncorresponding to the value preset in the register 36A₁ is employed andthe test is carried out, and the changed application mode (D₁, W₁, R₀)maintained until when the test pattern corresponding to the value presetin the register 36B₁ is employed and the test is carried out.

FIGS. 6a to 6d illustrate examples of the waveform of the input testpattern according to the apparatus of FIG. 5. Note, in this explanation,reference is made to only a pair of registers 36A₁ and 36B₁ and thecorresponding comparator 37₁, for simplicity.

FIGS. 6a and 6b correspond to FIGS. 4a and 4b. FIG. 6c shows the inputtest pattern when the contents of both of the registers 36A₁ and 36B₁are "0" and FIG. 6d shows the input test pattern when the content of theregister 36A₁ is "2" and the content of the register 36B₁ is "4". As isobvious from a comparison between FIGS. 6c and 6d, the mode ofapplication of the test pattern is kept in the changed application mode(D₁, W₁, R₀) from when the second test pattern is employed and the testis carried cut until the fourth test pattern is employed and the test iscarried out.

Although, in the above explanation, reference is made to only a pair ofregisters 36A₁ and 36A₂ and the corresponding comparator 37₁, it isapparent to those skilled in the art that a variety of modes ofapplication of the test pattern, i.e., a variety of multi-windowdesignation type tests can be realized by a suitably selection of thevalues to be preset in the registers 36A₁ ˜36A_(n) and 36B₁ ˜36B_(n).

As described above, according to the LSI tester of the presentinvention, by adding an external circuit or circuits having a simpleconstitution to a buffer memory the mode of application of the testpattern can be easily changed when the test is carried out with anarbitrary test pattern without increasing the capacity of the buffermemory. Also, the LSI tester according to this inventions makes a changein writing into the buffer memory unnecessary, and accordingly, enablesa more efficient test.

Although the present invention has been disclosed and described by wayof only two embodiments, it is apparent to those skilled in the art thatother embodiments and modifications of the present invention arepossible without departing from the spirit or essential featuresthereof.

I claim:
 1. A test apparatus for determining whether an integratedcircuit is functional or non-functional, said apparatus comprising:aclock generator for generating a train of clocks with a variable rate ofgeneration; a first memory in which instruction data, including specificinstructions indicating a loop control for repetitively applying a testpattern and a termination of the loop control, is preset and stored; asecond memory in which a plurality of input data and a correspondingplurality of expected output data are preset and stored; a patterncounter, connected to said clock generator, for sequentially countingsaid clocks output from said clock generator, one by one; a registercircuit having a plurality of registers in each of which a selecteddesignated value is preset and stored; a comparing circuit, connected tosaid pattern counter and said register circuit, comparing each of saiddesignated values in said register circuit with a value of said patterncounter and outputting control signals based on results of saidcomparison of each designated value and said counted clock value; atiming data outputting circuit connected to said comparing circuit, saidtiming data outputting circuit defining a) a plurality of first timingdata representing different time delays for a test pattern within a timeinterval defined by said variable rate, b) a plurality of second timingdata representing different pulse widths, and c) a plurality of rateinformation indicating different time intervals defined by said variablerate, said timing data outputting circuit outputting one of said firsttiming data, one of said second timing data and one of said rateinformation in response to said control signals from said comparingcircuit wherein said test pattern varies based on the first and secondtiming data and rate information output therefrom; control meansconnected to said first memory, said second memory, said clock generatorand said timing data outputting circuit, said control means for changinga rate of generation of said clocks based on said rate informationoutput from the timing data outputting circuit, for reading saidinstruction data from said first memory in response to each of theclocks with the changed rate of generation, for causing said secondmemory to output said input data and said corresponding expected outputdata in accordance with the content of said instruction data, and forcontrolling the second memory to effect the loop control forrepetitively outputting the input data and the corresponding expectedoutput data and the termination of the loop control in accordance withsaid specific instructions; and a testing circuit connected between saidsecond memory and said integrated circuit to be tested, for applyingsaid input data from said second memory to said integrated circuit basedon said first and second timing data and comparing a signal output fromsaid integrated circuit in response to said input data with saidexpected output data, corresponding to said input data, from said secondmemory, wherein a result of a determination of whether said integratedcircuit is functional or non-functional is indicated.
 2. An apparatus asset forth in claim 1, wherein said control means comprises a controllerfor reading said instruction data from said first memory in response toeach of said clocks output from said clock generator and decoding thecontent of said instruction data, and an address counter for changing anaddress information therein based on said decoded content and causingsaid second memory to output an input data indicated by said changedaddress information and a corresponding expected output data.
 3. Anapparatus as set forth in claim 1, wherein a capacity of said firstmemory is smaller than a capacity of said second memory.
 4. An apparatusas set forth in claim 1, wherein said comparing circuit comprises acomparator and said register circuit comprises a corresponding register,said comparator comparing a designated value stored in the correspondingregister with a value of said pattern counter and outputting a firstcontrol signal when a result of said comparison indicates anon-coincidence of said values and a second control signal when saidresult indicates a coincidence of said values.
 5. An apparatus as setforth in claim 4, wherein said timing data outputting circuit outputsone of said second timing data in response to said second control signaland outputs said first timing data in response to said first controlsignal.
 6. An apparatus as set forth in claim 1, wherein said comparingcircuit comprises a plurality of comparators and said register circuitcomprises a corresponding plurality of registers, each of saidcomparators comparing a designated value stored in a correspondingregister with a value of said pattern counter and outputting a firstcontrol signal when a result of said comparison indicates anon-coincidence of said values and a second control signal when saidresult indicates a coincidence of said values.
 7. An apparatus as setforth in claim 6, wherein said timing data outputting circuit outputsone of said second timing data in response to said second control signaland outputs said first timing data in response to said first controlsignal.
 8. An apparatus as set forth in claim 1, wherein said comparingcircuit comprises a comparator and said register circuit comprises acorresponding pair of registers, said comparator comparing a pair ofdesignated values stored in the corresponding pair of registers with avalue of said pattern counter and, based on said comparison, outputtinga first control signal when said value of said pattern counter is out ofthe range defined said pair of designated values and a second controlsignal when said value is within said range.
 9. An apparatus as setforth in claim 8, wherein said timing data outputting circuitcontinuously outputs said second timing data in response to said secondcontrol signal and continuously outputs said first timing data inresponse to said first control signal.
 10. An apparatus as set forth inclaim 1, wherein said comparing circuit comprises a plurality ofcomparators and said register circuit comprises a correspondingplurality of pairs of registers, each of said comparators comparing apair of designated values stored in the corresponding pair of registerswith a value of said counter and, based on said comparison, outputting afirst control signal when said value of said counter is out of the rangedefined by said pair of designated values and a second control signalwhen said value is within said range.
 11. An apparatus as set forth inclaim 10, wherein said timing data outputting circuit continuouslyoutputs one of said second timing data in response to said secondcontrol signal and continuously outputs said first timing data inresponse to said first control signal.
 12. A test apparatus fordetermining whether an integrated circuit is functional ornon-functional, said apparatus comprising:a clock generator forgenerating a train of clocks with a variable rate of generation; a firstmemory in which instruction data is preset and stored; a second memoryin which a plurality of input data and a corresponding plurality ofexpected output data are preset and stored; a pattern counter forsequentially counting said clocks output from said clock generator, oneby one; a register circuit having a plurality of registers in each ofwhich a selected designated value is preset and stored; a comparingcircuit, connected to said pattern counter and said register circuit,comparing each of said designated values in said register circuit with avalue of said pattern counter and outputting control signals based onresults of said comparison of each designated value and said countedclock value; a timing data outputting circuit connected to saidcomparing circuit, said timing data outputting circuit defining a) aplurality of first timing data representing different first applicationmodes of a test pattern within a time interval defined by said variablerate, b) a plurality of second timing data representing secondapplication modes different from said first application modes, and c) aplurality of rate information indicating different time intervalsdefined by said variable rate, said timing data outputting circuitoutputting one of said first timing data, one of said second timing dataand one of said rate information in response to said control signalsfrom said comparing circuit wherein said test pattern varies based onthe first and second timing data and rate information output therefrom;control means connected to said first memory, said second memory, saidclock generator and said timing data outputting circuit, said controlmeans for changing a rate of generation of said clocks based on saidrate information output from the timing data outputting circuit, and forcausing said second memory to output said input data and saidcorresponding expected output data in accordance with the content ofsaid instruction data; and a testing circuit connected between saidsecond memory and said integrated circuit to be tested, for applyingsaid input data from said second memory to said integrated circuit basedon said first and second timing data and comparing a signal output fromsaid integrated circuit in response to said input data with saidexpected output data, corresponding to said input data, from said secondmemory, wherein a result of a determination of whether said integratedcircuit is functional or non-functional is indicated.